View ADSP-21535P_2863447.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

a preliminary technical data this information applies to a product under development. its characteristics and speci- fications are subject to change without notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. one technology way, p.o.box 9106, norwood, ma 02062-9106, u.s.a. tel:781/329-4700 www.analog.com fax:781/326-8703 ?analog devices,inc., 2002 rev. prc preliminary technical data adsp-21535 summary 300 mhz high-performance blackfin dsp core two 16-bit macs, two 40-bit alus, two 40-bit accumulators, four 8-bit video alus, and a 40-bit shifter risc-like register and instruction model for ease of programming and compiler-friendly support advanced debug, trace, and performance- monitoring 0.9?1.5 v core v dd with dynamic power management 3.3 v i/o 0oc to +85oc case commer cial temperature range -40oc to +105oc case industrial temperature range (200 mhz) 260-lead pbga package memory 4g-byte unified address range 308k bytes of on-chip memory: 16k bytes of instruction sram/cache 32k bytes of data sram/cache 4k bytes of scratchpad sram 256k bytes of full speed, low latency sram memory dma controller memory mgmt unit providing memory protection glueless external memory controllers synchronous sdram support asynchronous with sram, flash, rom support peripherals 32-bit, 33-mhz, 3.3 v, pci 2.2-compliant bus interface with master and slave support integrated usb 1.1-compliant device interface two uarts, one with irda? two spi-compatible ports two full-duplex synchronous serial ports (sports) functional block diagram system bus interface unit dma controller blackfin core pci bus interface 256k bytes sram 64 interrupt controller/ timer real time clock uart port 1 uart port 0 irda ? timer0, timer1, timer2 programmable flags usb interface serial ports (2) spi ports (2) external port boot rom 32 32 32 32 jtag test and emulation watchdog timer flash sdram control 32
for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 2 rev. prc preliminary technical data four timer/counters, three with pwm support sixteen bi-directional pr ogrammable flag i/o pins watchdog timer real-time clock on-chip pll with 1x to 31x frequency multiplier general note this data sheet provides pr eliminary information for the adsp-21535 blackfin dsp. general description the adsp-21535 is a member of the blackfin dsp family of products, incorporating th e micro signal architecture (msa), jointly developed by analog devices, inc. and intel corporation. the architect ure combines a dual-mac state-of-the-art dsp engine, the advantages of a clean, orthogonal risc-like micropro cessor instruction set, and single-instruction, multiple-data (simd) multimedia capa- bilities into a single in struction set architecture. by integrating a rich set of industry leading system periph- erals and memory, blackfin dsps are the platform of choice for next generation applications that require risc like pro- grammability, multimedia supp ort and leading edge signal processing in one integrated dsp. portable low-power architecture blackfin dsps provide world class power dissipation and performance compared to othe r digital signal processors. blackfin dsps are designed in a low-power and low-volt- age design methodology and feature dynamic power management, the ability to vary both the voltage and frequency of operation to significantly lower overall power consumption. varying the voltage and frequency can result in a three-fold reduction in power consumption, by com- parison to just varying the frequency of operation. this translates into longer batter y life for portable appliances. system integration the adsp-21535 is a highly in tegrated system-on-a-chip solution for the next generation of digital communication and portable internet appl iances. by combining indus- try-standard interfaces with a high performance digital signal processing core, user s can develop cost effective solutions quickly without the n eed for costly external com- ponents. the adsp-21535 sy stem peripherals include uarts, spis, sports, general purpose timers, a real-time clock, programmable flags, watchdog timer, and usb and pci buses for glueless peripheral expansion. adsp-21535 peripherals the adsp-21535 contains a rich set of peripherals connected to the core via se veral high bandwidth buses, providing flexibility in system configuration as well as excellent overall system perfor mance. see functional block diagram on page 1. the base peripherals include general purpose functions such as uarts, timers with pwm (pulse width modulator) an d pulse measur ement capabil- ity, general purpose flag i/o pins, a real-time clock, and a watchdog timer. this set of functions satisfies a wide variety of typical system supp ort needs and is augmented by the system expansion capabilities of the part. in addition to these general-purpose pe ripherals, the adsp-21535 contains high speed serial ports for interfaces to a variety of audio and modem codec functions. it also contains an event handler for flexible mana gement of interrupts from the on-chip peripherals and external sources and power management control functions to tailor the performance and power characteristics of the processor and system to many application scenarios. the on-chip peripherals can be easily augmented in many system designs with little or no glue logic due to the inclusion of several interfaces providing expa nsion on indus- try-standard buses. these include a 32-bit, 33-mhz, v2.2-compliant pci bus, spi serial expansion ports and a device type usb port. these enable the connection of a large variety of peripheral devi ces to tailor the system design to specific applications wi th a minimum of design complexity. all of the peripherals, exce pt for programmable flags, real-time clock, and timers, are supported by a flexible dma structure with individual dma channels integrated into the peripherals. there is also a separate memory dma channel dedicated to data transfers between the dsp's various memory spaces incl uding external sdram and asynchronous memory, internal level 1 and level 2 sram and pci memory spaces. multiple on-chip 32-bit buses running at up to 133 mhz provide adequate bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals. blackfin dsp core as shown in figure 1 , the blackfin dsp core contains two multiplier/accumulators (macs), two 40-bit alus, four video alus, and a single shifter. the computational units process 8-bit, 16-bit, or 32-bit data from the register file. each mac performs a 16-bit by 16-bit multiply in every cycle, with an accumulation to a 40-bit result, providing 8 bits of extended precision. the alus perform a standard set of arithmetic and logical operations. with two alus capable of operating on 16- or 32-bit data, the flexibility of the computation units covers the signal processing requiremen ts of a varied set of appli- cation needs. each of the tw o 32-bit input registers can be regarded as two 16-bit halves , so each alu can accomplish very flexible single 16-bit arit hmetic operations. by viewing the registers as pairs of 16-bit operands, dual 16-bit or single 32-bit operations can be accompli shed in a single cycle. by further taking advantage of the second alu, quad 16-bit operations can be a ccomplished simply, accelerating the per cycle throughput. the powerful 40-bit shifter has extensive capabilities for performing shifting, rotating, normalization, extraction, and depositing of data.
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 3 rev. prc for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 preliminary technical data the data for the computational units is found in a multi-ported register file of sixteen 16-bit entries or eight 32-bit entries. a powerful program sequencer co ntrols the flow of instruc- tion execution, including instruction alignment and decoding. the sequencer sup ports conditional jumps and subroutine calls, as well as zero-overhead looping. a loop buffer stores instructions locally, eliminating instruction memory accesses for tight looped code. two data address generators (dags) provide addresses for simultaneous dual operand fetches from memory. the dags share a register file cont aining four sets of 32-bit index, modify, length, and base registers. eight additional 32-bit registers provide pointers for general indexing of variables and stack locations. blackfin dsps support a modi fied harvard architecture in combination with a hi erarchical memory structure. level 1 (l1) memories are those that typically operate at the full processor speed with little or no latency. level 2 (l2) memories are other memories, on-chip or off-chip, that may take multiple processo r cycles to access. at the l1 level, the instruction memory holds instructions only. the two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information. at the l2 level, there is a single unified memory space, holding both instructions and data. in addition, the l1 instruction memory and l1 data memories may be configured as either static rams (srams) or caches. the me mory management unit (mmu) provides memory protection for individual tasks that may be operating on the core and may protect system registers from un intended access. the architecture provides thr ee modes of operation: user mode, supervisor mode, and emulation mode. user mode has restricted access to certa in system resources, thus providing a protected software environment, while supervi- sor mode has unrest ricted access to th e system and core resources. the blackfin dsp instruction set has been optimized so that 16-bit op-codes represent the mo st frequently used instruc- tions, resulting in excellent compiled code density. complex dsp instructions ar e encoded into 32-b it op-codes, repre- senting fully featured multifunction instructions. blackfin dsps support a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instructions, allowing the prog rammer to use many of the core resources in a single instruction cycle. the blackfin dsp assembly language uses an algebraic syntax for ease of coding an d readability. th e architecture has been optimized for use in conjunction with the c-com- piler, resulting in fast and efficient software implementations. figure 1. blackfin dsp core sp seq ue ncer align decode loop buffer dag0 dag1 16 16 8 888 40 40 a0 a1 barrel shifter data arithme tic uni t control unit address arithmetic unit fp p5 p4 p3 p2 p1 p0 r7 r6 r5 r4 r3 r2 r1 r0 i3 i2 i1 i0 l3 l2 l1 l0 b3 b2 b1 b0 m3 m2 m1 m0
for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 4 rev. prc preliminary technical data memory architecture the adsp-21535 views memory as a single unified 4g-byte address space, using 32- bit addresses. all resources including internal memory, ex ternal memory, pci address spaces, and i/o control register s occupy separa te sections of this common addr ess space. the memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low-latency memory as cache or sram very close to the processor, and larger, lower- cost and performance-memory systems farther away from the processor. see figure 2 . the l1 memory system is th e primary highest-performance memory available to the blackfin dsp core. the l2 memory provides additional ca pacity with slightly lower performance. lastly, the off- chip memory system, accessed through the external bus interface unit (ebiu), provides expansion with sdram, flash memory, and sram, optionally accessing more th an 768m bytes of physical memory. the memory dma controller provides high-bandwidth data-movement capability. it can perform block transfers of code or data between the internal l1/l2 memories and the external memory spaces (inc luding pci memory space). internal (on-chip) memory the adsp-21535 has four blocks of on-chip memory providing high-bandwidth access to the core. the first is the l1 instruct ion memory consisting of 16k bytes of 4-way set-asso ciative cache memory. in addition the memory may be configured as an sram. this memory is accessed at full processor speed. the second on-chip memory bl ock is the l1 data memory, consisting of two banks of 16k bytes each. each l1 data memory bank can be configured as one way of a two-way set associative cache or as an sram, and is accessed at full speed by the core. the third memory block is a 4k-byte scratchpad ram which runs at the same speed as the l1 memories, but is only accessible as data sram (it cannot be configured as cache memory and is no t accessible via dma). the fourth on-chip memory system is the l2 sram memory array which provides 256k bytes of high speed sram at the full bandwidth of the core, and slightly longer latency than the l1 memory banks. the l2 memory is a unified instruction and data memory and can hold any mixture of code and data required by the system design. the blackfin dsp core has a dedicated low-latency 64-bit wide datapath port into the l2 sram memory. for example, at a core frequency of 300 mhz, the peak data transfer rate across this interface is up to 2.4g bytes per second. external (off-chip) memory external memory is accessed vi a the external bus interface unit (ebiu). this interface pr ovides a glueless connection to up to four banks of synchronous dram (sdram) as figure 2. internal/external memory map core mmr registers (2m byte) i n t e r n a l m e m o r y m a p reserved scratchpad sram (4k byte) instruction sram (16k byte) system mmr registers (2m byte) reserved reserved data ban k b sram ( 16 k byt e) reserved data ban k a sram ( 16 k byt e) reserved l2 sram memory (256k byte) reserved e x t e r n a l m e m o r y m a p pci config space port (4 byte) pci config registers (64k byte) reserved pci io space (64k byte) reserved pci memory space (128m byte) reserved async memory bank 3 (64m byte) async memory bank 2 (64m byte) async memory bank 1 (64m byte) async memory bank 0 (64m byte) sdram memory bank 3 (16m byte - 128m byte) * sdram memory bank 2 (16m byte - 128m byte) * sdram memory bank 1 (16m byte - 128m byte) * sdram memory bank 0 (16m byte - 128m byte) * 0xffff ffff 0xffe0 0000 0xffb0 0000 0xffa0 4000 0xffa0 0000 0xff90 4000 0xff90 0000 0xff80 4000 0xff80 0000 0xf003 ffff 0xf000 0000 0xef00 0000 0xeeff fffc 0xeeff ff00 0xeefe ffff 0xeefe 0000 0xe7ff ffff 0xe000 0000 0x2fff ffff 0x2c00 0000 0x2800 0000 0x2400 0000 0x2000 0000 0x1800 0000 0x1000 0000 0x0800 0000 0x0000 0000 0xffc0 0000 0xffb0 1000 * the addresses shown for the sdram banks reflect a fully populated sdram array with 512m bytes of memory. if any bank contains less than 128m bytes of memory, that bank would extend only to the length of the real memory systems, and the end address would become the start address of the next bank. this would continue for all four banks, with any remaining space between the end of memory bank 3 and the beginning of async memory bank 0, at address 0x2000 0000, treated as reserved address sp a ce.
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 5 rev. prc for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 preliminary technical data well as up to four banks of asynchronous memory devices including flash, eprom, rom, sram, and memory mapped i/o devices. the pc133-complian t sdram controller can be pro- grammed to interface to up to four banks of sdram, with each bank containing be tween 16m bytes and 128m bytes providing access to up to 512m bytes of sdram. each bank is independently programmable and is contiguous with adjacent banks regardless of the sizes of the different banks or their placement. this allows flexible configuration and upgradability of system memory while allowing the core to view all sdram as a single, contiguous, physical address space. the asynchronous memory co ntroller can also be pro- grammed to control up to four banks of devices with very flexible timing parameters for a wide variety of devices. each bank occupies a 64m-b yte segment regardless of the size of the devices used so that these banks will only be contiguous if fully populated with 64m bytes of memory. pci the pci bus defines three separate address spaces, which are accessed through windows in the adsp-21535 memory space. these are pci memory, pci i/o, and pci configu- ration space. in addition, the pci interface ca n either be used as a bridge from the processor core as the controlling cpu in the system, or as a host port where another cpu in the system is the host and the adsp-21535 is functioning as an intel- ligent i/o device on the pci bus. when the adsp-21535 acts as the system controller, it views the pci addres s spaces through its mapped windows and can initialize all devices in the system and maintain a map of the topology of the environment. the pci memory region is a 4g -byte space that appears on the pci bus and can be used to map memory i/o devices on the bus. the adsp-21535 uses a 128m-byte window in memory space to see a portio n of the pci memory space. a base address register is provided to position this window anywhere in the 4g-byte pc i memory space while its position with respect to th e processor addresses remains fixed. the pci i/o region is also a 4g-byte space. however, most systems and i/o devices only us e a 64k-byte subset of this space for i/o mapped addr esses. the adsp-21535 imple- ments a 64k-byte window into this space along with a base address register which can be used to position it anywhere in the pci i/o address space, while the window remains at the same address in the processor's address space. pci configuration space is a li mited address space, which is used for system enum eration and initialization and which is a very low-performance commu nication mode between the processor and pci devices. the adsp-21535 provides a one-value window to access a single data value at any address in pci configuration space. this window is fixed and receives the address of the value, and the value if the operation is a write. otherwise the device returns the value into the same address on a read operation. i/o memory space blackfin dsps do not define a separate i/o space. all resources are mapped through th e flat 32-bit address space. on-chip i/o devices have thei r control registers mapped into memory-mapped registers (mmrs) at addresses near the top of the 4g-byte addres s space. these are separated into two smaller blocks, one which contains the control mmrs for all core functions, and the other which contains the registers needed for setu p and control of the on-chip peripherals outside of the co re. the core mmrs are acces- sible only by the core and on ly in supervisor mode and appear as reserved space by on-chip peripherals, as as well as external devices accessing resources through the pci bus. the system mmrs are accessible by the core in supervisor mode and can be mapped as ei ther visible or reserved to other devices, depending on the system protection model desired. booting the adsp-21535 contains a smal l boot kernel, which con- figures the appropriate peripheral for booting. if the adsp-21535 is configured to boot from boot rom memory space, the dsp starts executing from the on-chip boot rom. for more information, see booting modes on page 14 . event handling the event controller on the adsp-21535 handles all asyn- chronous and synchronous even ts to the processor. the adsp-21535 provides event hand ling that supports both nesting and prioritization. nesting allows multiple event service routines to be active simultaneously. prioritization ensures that servicing of a higher-priority event takes pre- cedence over servicing of a lower-priority event. the controller provides support for five different types of events: ? ? ?
for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 6 rev. prc preliminary technical data ? ? core event controller (cec) the cec supports nine general-purpose interrupts (ivg15?7), in addition to the dedicated interrupt and exception events. of these ge neral-purpose interrupts, the two lowest-priority interrupts (ivg15?14) are recom- mended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the adsp-21535. table 1 describes the inputs to the cec, id entifies their names in the event vector table (evt), and list s their priorities. system interrupt controller (sic) the system interrupt controll er provides the mapping and routing of events from the many peripheral interrupt sources, to the prioritized gene ral-purpose interrupt inputs of the cec. although the adsp-21535 provides a default mapping, the user can alter th e mappings and priorities of interrupt events by writing th e appropriate values into the interrupt assignment registers (iar). table 2 describes the inputs into the sic and the default mappings into the cec. event control the adsp-21535 provides the us er with a very flexible mechanism to control the processing of ev ents. in the cec, three registers are used to co ordinate and control events. each of the registers,as follow s, is 16-bits wide, while each bit represents a particular event class: ? ?
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 7 rev. prc for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 preliminary technical data is unmasked and will be pr ocessed by the system when asserted. a cleared bit in th e imask register masks the event thereby preventing the processor from servicing the event even though the event may be latched in the ilat register. this register may be read from or written to while in supervisor mode. (note that general-purpose inter- rupts can be globally enable d and disabled with the sti and cli instructio ns, respectively.) ? ? ? ?
for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 8 rev. prc preliminary technical data a set of programmable timing parameters is available to configure the sdram banks to support slower memory devices. the memory banks can be configured as either 32-bits wide for maximum performance and bandwidth or 16-bits wide for minimum de vice count and lower system cost. all four banks share common sdram control signals and have their own bank select lines providing a completely glueless interface for most system configurations. asynchronous controller the asynchronous memory cont roller provides a config- urable interface for up to four separate banks of memor y or i/o devices. each bank can be independently programmed with different timing paramete rs, enabling connection to a wide variety of memory devices including sram, rom, and flash eprom, as well as i/o devices that interface with standard memory control lin es. each bank occupies a 64m-byte window in the processor?s addr ess space but, if not fully populated, these are not made contiguous by the memory controller logic. the banks can also be configured as 16-bit wide or 32-bit wide bu ses for ease of interfacing to a range of memories and i/o devi ces tailored either to high performance or to low cost and power. pci interface the adsp-21535 provides a gluele ss logical and electrical, 33-mhz, 3.3 v, 32-bit pci (peripheral component inter- connect), revision 2.2-comp liant interface. the pci interface is designed for a 3- volt signalling environment. the pci interface provides a bus bridge function between the processor core and on-chip peripherals and an external pci bus. the pci interface of the adsp-21535 supports two pci functions, as follows ? ?
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 9 rev. prc for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 preliminary technical data when enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. there are two alarms: the first alarm is for a time of day. the second alarm is for a day and time of that day. the stopwatch function counts down from a programmed value, with one minute resolu tion. when the stopwatch is enabled and the counter underflows, an interrupt is generated. like the other peripherals, the rtc can wake up the adsp-21535 processor from a low-power state upon gen- eration of any interrupt. connect rtc pins xtali and xtalo with external com- ponents, as shown in figure 3 . watchdog timer the adsp-21535 includes a 32-bit timer, which can be used to implement a softwa re watchdog function. a software watchdog can improve system availability by forcing the processor to a known state, via generation of a hardware reset, no n-maskable interrupt (nmi), or gen- eral-purpose interrupt, if the timer expires before being reset by software. the progra mmer initializes the count value of the timer, enables th e appropriate interrupt, then enables the timer. thereafter, the software must reload the counter before it counts to zero from the programmed value. this protects the system from remaining in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error. after a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the timer control register , which is set only upon a watchdog generated reset. the timer is clocked by the system clock (sclk), at a maximum frequency of f sclk . timers there are four programmab le timer units in the adsp-21535. three general-purpose timers have an external pin that can be configured either as a pulse width modulator (pwm) or timer output, as an input to clock the timer, or for measuring pulse wi dths of external events. each of the three general-purpose timer units can be indepen- dently programmed as a pwm, internally or externally clocked timer, or pulse width counter. the general-purpose timer units can be used in conjunction with the uarts to measure the width of the pulses in the data stream to provide an auto-baud detect function for a serial channel. the general-purpose timers can generate interrupts to the processor core providing peri odic events for synchroniza- tion, either to the processor cl ock or to a count of external signals. in addition to the three ge neral-purpose programmable timers, a fourth timer is also provided. this extra timer is clocked by the internal pro cessor clock (c clk) and is typically used as a system ti ck clock for generation of operating system periodic interrupts. serial ports (sports) the adsp-21535 incorporates two complete synchronous serial ports (sport0 and sport1) for serial and multi- processor communications. the sports support the following features: ? ? ? ? ? ? ? figure 3. external components for rtc xta l i x1 xta l o c1 c2 suggested components: ecliptek ec38j (through-hole package) epson mc-405 12.5 pf load (surface mount package) c1 = 22 pf c2 = 22 pf note: c1 and c2 are specific to crystal specified for x1. contact crystal manufacturer for details. c1 and c2 specifications assume board trace capacitance of 3 pf.
for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 10 rev. prc preliminary technical data sequences of dma transfers between a sport and memory. the chained dma can be dynamically allocated and updated through the descriptor blocks that set up the chain. ? ? spissx spi dsp, spi spixsel71 dsp spi t spi p f u , spi x, , e spi f 4 , dma , t spi dma d , spi t i , dsp spi 1 e spi , 2 s spi spixsel p f 3 d tcb dsp dma 4 e spi dma dma 5 i -dma , spi t sckx mosix misox i dma , spi dma 1 0 i , dsp spi 1 e spi spi 2 d tcb dsp - dma 3 e spi dma dma 4 s spi sckx spi spissx p f i dma , spi dma 1 0 t dsp , x tcb a , x dsp , tcb, spi i spi , uart port t adsp-21535 x u a- rt uart uart0 uart1 pc- uart t uart uart , x, dma , e uart 5 1 2 , , t uart , ? ? figure 4. spi clock rate calculation spi clock rate f sclk 2 spibaud
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 11 rev. prc for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 preliminary technical data each uart port?s baud rate (see figure 5 ), serial data format, error code generation and status, and interrupts are programmable: ? ? ? ? ? ? ? figure 5. uart clock rate calculation 1 1 where d = 1 to 65536 uart clock rate f sclk 16 d
for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 12 rev. prc preliminary technical data sleep operating mode ? high power savings the sleep mode reduces power dissipation by disabling the clock to the processor core (cclk). the pll and system clock (sclk) however, continue to operate in this mode. any interrupt, typically via some external event or rtc activity, will wake up the pr ocessor. when in the sleep mode, assertion of any interrup t will cause the processor to sense the value of the bypass bit (bypass) in the pll control register (pll_ctl). if bypass is disabled, the processor will transition to the full on mode. if bypass is enabled, the processor will tran sition to the active mode. when in the sleep mode, system dma access to l1 memory is not supported. deep-sleep operating mode ? maximum power savings the deep-sleep mode maxi mizes power savings by disabling the clocks to the pr ocessor core (cclk) and to all synchronous systems (sclk). asynchronous systems, such as the rtc, may still be running but will not be able to access internal resources or external memory. this powered down mode can only be exited by assertion of the reset interrupt ( reset rtc w d-s , reset bypass i , f o i , a w d-s , rtc f o , bypass t deepsleep m t t f 6 pllctl x pll t , , n dma p s a t 4 , adsp-21535 t x x, - b adsp-21535 , pll, rtc, pci, io, - , pll, rtc, io t f x, 25 25 - , 25 40 f, , d p m ddint clk a x , p d f cclkred cclknom (v ddintred /v ddintnom ) 2 where ? ? ? ?
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 13 rev. prc for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 preliminary technical data peripheral power control the adsp-21535 provides addi tional power control capa- bility by allowing dynamic schedu ling of clock inputs to each of the peripherals. clocking to each of the peripherals listed below can be enabled or disabled by appropriately setting the peripheral?s control bit in the peripheral clock enable register (pll_iock). the peripheral clock enable register allows individual control for each of the following peripherals: ? ? ? ? ? ? ? ? ? ? ? ? adsp-21535 dsp hardware reference . the peripheral clock is supplied to the clkout_sclk0 pin. figure 6. mode transitions sleep full-on active d e e p s l e e p reset wakeup & bypass=0 stopck=1 & pdwn=0 pdwn=1 rtc_wakeup pdwn=1 stopck=1 & pdwn=0 hardware reset bypass=0 & pll_off=0 & stopck=0 & pdwn=0 bypass=1 & stopck=0 & pdwn=0 msel=new & pll_off=0 & bypass=1 msel=new & pll_off=0 & bypass=0 wakeup & bypass=1
for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 14 rev. prc preliminary technical data all on-chip peripherals operate at the rate set by the system clock (sclk). the system cl ock frequency is programma- ble by means of the ssel pins. at run time the system clock frequency can be controlled in software by writing to the ssel fields in the pll contro l register (pll_ctl). the values programmed into the ss el fields define a divide ratio between the core clock ( cclk) and the system clock. table 5 illustrates the system clock ratios. the maximum frequency of the system clock is f sclk . note that the divisor ratio must be ch osen to limit th e system clock frequency to its maximum of f sclk . the reset value of the ssel1?0 is determined by sampling the programmable flag input pins (pf9?8) during reset. the ssel value can be changed dynamically by wr iting the appropriate values to the pll control register (p ll_ctl), as described in the adsp-21535 dsp hardware reference . booting modes the adsp-21535 has three mechanisms (listed in table 6 ) for automatically loading internal l2 memory after a reset. a fourth mode is provided to execute from external memory, bypassing the boot sequence. the bmode pins of the reset configuration register, sampled during power on resets and software initiated resets, implement the following modes: ? ? ? ? figure 7. clock ratio example table 5. system clock ratios signal name ssel1? 0 divider ratio cclk/ sclk example frequency ratios (mhz) cclk sclk 00 01 10 11 2:1 2.5:1 3:1 4:1 266 275 300 300 133 110 100 75 clkin clkout adsp-21535 msel5 (pf5) msel4 (pf4) msel3 (pf3) msel2 (pf2) msel1 (pf1) msel0 (pf0) reset msel6 (pf6) df (pf7) v dd v dd bypass reset source the pull-up/pull- down resistors on the msel, df, and bypass pins select the core clock ratio. here, the selection (6:1) and 25mhz input clock produce a 150mhz core clock. table 6. booting modes bmode2?0 description 000 001 010 011 100 ?111 execute from 16-bit external memory (bypass boot rom) boot from 8-bit flash boot from spi0 serial rom (8-bit address range) boot from spi0 serial rom (16-bit address range) reserved
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 15 rev. prc for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 preliminary technical data in addition, the reset configuration register can be set by application code to bypass th e normal boot sequence during a software reset. for this case , the processor jumps directly to the beginning of l2 memory space. to augment the boot modes de scribed above, a secondary software loader is provided that adds additional booting mechanisms. this seco ndary loader provid es the capability to boot from 16-bit flash memory, fast flash, variable baud rate, etc. instruction set description the blackfin dsp family assembly language instruction set employs an algebraic syntax th at was designed for ease of coding and readability. the inst ructions have been specifi- cally tuned to provide a flexible, densely encoded instruction set that compiles to a very small final memory size. the instruction set also provides fully featured multi- function instructions that allow the programmer to use many of the dsp core resources in a single instruction. coupled with many features more often seen on microcon- trollers, this instruction set is very efficient when compiling c and c++ source code. in addition, the architecture supports both a user (algorithm/application code) and a supervisor (o/s kernel, device drivers, debuggers, isrs) mode of operations, allowing multiple levels of access to core dsp resources. the assembly language, which takes advantage of the pro- cessor?s unique ar chitecture, offers the following advantages: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 16 rev. prc preliminary technical data the visualdsp++ kern el (vdk) incorporates scheduling and resource management tailor ed specifically to address the memory and timing constraints of dsp programming. these capabilities enable engi neers to develop code more effectively, eliminating the need to start from the very begin- ning, when developing new application code. the vdk features include threads, critical and unscheduled regions, semaphores, events , and device flags. the vdk also supports priority-based, pre-emptive, cooperative and time -sliced scheduling appr oaches. in addition, the vdk was designed to be scalable. if the application does not use a specific feature, the support code for that feature is excluded from th e target system. because the vdk is a library, a developer can decide whether to use it or not. th e vdk is integrated into the visualdsp++ development envi ronment, but can also be used via standard command li ne tools. when the vdk is used, the development enviro nment assists the developer with many error-prone tasks and assists in managing system resources, automating the generation of various vdk based objects, and visualizing the sy stem state, when debugging an application that uses the vdk. analog devices? dsp emulators use the ieee 1149.1 jtag test access port of the adsp -21535 to monitor and control the target board processor duri ng emulation. the emulator provides full-speed emulatio n, allowing inspection and modification of memory, registers, and processor stacks. nonintrusive in-circuit emulat ion is assured by the use of the processor?s jtag interf ace?the emulator does not affect target system loading or timing. in addition to the software and hardware development tools available from analog devices, third parties provide a wide range of tools supporting the blackfin dsp family. hardware tools include th e adsp-21535 ez-kit lite? standalone evaluation/devel opment cards. third party software tools include dsp li braries, real-time operating systems, and block diagram design tools. designing an emulator-compatible dsp board (target) the analog devices family of emulators are tools that every dsp developer needs to test and debug hardware and software systems. analog devices has supplied an ieee 1149.1 jtag test access port (tap) on the adsp-21535. the emulator uses the tap to access the internal features of the dsp, allowing the developer to load code, set break- points, observe variables, observe memory, and examine registers. the dsp must be halted to send data and commands, but once an operat ion has been completed by the emulator, the dsp system is set running at full speed with no impact on system timing. to use these emulators, the targ et?s design must include the interface between an analog devices? jtag dsp and the emulation header on a cu stom dsp target board. target board header the emulator interface to an analog devices? jtag dsp is a 14-pin header, as shown in figure 8 . the customer must supply this header on the ta rget board in order to commu- nicate with the emulator. th e interface consists of a standard dual row 0.025" sq uare post header, set on 0.1" 0.1" spacing, with a mini mum post length of 0.235". pin 3 is the key position used to prevent the pod from being inserted backwards. this pin mu st be clipped on the target board. also, the clearance (length, wi dth, and height) around the header must be considered. le ave a clearance of at least 0.15" and 0.10" around the leng th and width of the header, and reserve a height clearance to attach and detach the pod connector. as can be seen in figure 8 , there are two sets of signals on the header. there are the standard jtag signals tms, tck, tdi, tdo, trst , emu t tag btms, btck, btdi, btrst - - w , btms, btck, btrst , btdi f t tag dsp r tag jtag emulator pod connector figure 10 details the dimensions of the jtag pod connector at the 14-pin target end. figure 11 displays the keep-out area for a target board header. the keep-out area allows the pod connector to properly seat onto the target board header. figure 8. jtag target bo ard connector for jtag equipped analog devices dsp (jumpers in place) top view 13 14 11 12 910 78 56 34 12 emu gnd tms tck trst tdi tdo gnd key (no pin) btms btck btrst btdi gnd
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 17 rev. prc for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 preliminary technical data this board area should cont ain no components (chips, resistors, capacitors, etc.). the dimensions are referenced to the center of the 0.25" square post pin. design-for-emulation circuit information for details on target board design issues including: single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the ee-68: analog devices jtag emulation technical reference on the analog devices website (www.ana- log.com)?use site search on ?ee-68?. this document is updated regularly to keep pace with improvements to emulator support. additional information this data sheet provides a general overview of the adsp-21535 architecture and fu nctionality. for detailed information on the blackfin dsp family core architecture and instruction set, refer to the adsp-21535 hardware reference and the blackfin dsp family instruction set reference . figure 9. jtag target boar d connector with no local boundary scan figure 10. jtag pod connector dimensions top view 13 14 11 12 910 9 78 56 34 12 emu gnd tms tck trst tdi tdo gnd key (no pin) btms btck btrst btdi gnd 0.64" 0.88" 0.24" figure 11. jtag pod connector keep-out area 0.10" 0.1 5"
for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 18 rev. prc preliminary technical data pin descriptions adsp-21535 pin definitions are listed in table 7 . the following pins are asyn chronous: ardy, pf15?0, usb_clk, nmi, trst, reset, pci_clk, xtali, xtalo. the following symbols appear in the type column of table 7 : i = input, o = output, t = three-state, p = power, and g = ground. table 7. pin descriptions pin type function addr25?2 o/t external address bus. data31 ? 0 1 i/o/t external data bus. abe sdqm30 ot a , sdram ams3C0 ot c ardy 1, 2 i a aoe ot m are o r awe ow clkout sclk1 o sdram s sclk0 p sclk0 c sdram ck sclk0 o sdram 0 s c sdram ck scke ot sdram c sdram cke sa10 ot sdram a10 sdram sdram c sdram a10 sras ot sdram c sdram ras scas ot sdram c sdram cas swe ot sdram c sdram we w sms3C0 ot m x sdram c sdram tmr0 2 iot t 0 f pwmout widt_cnt ext_clk tmr1 2 iot t 1 f pwmout widt_cnt ext_clk tmr2 2 iot t 2 f pwmout widt_cnt ext_clk pf15 spi1sel7 2 iot p spi pf14 spi0sel7 2 iot p spi pf13 spi1sel6 2 iot p spi
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 19 rev. prc for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 preliminary technical data pf12 / spi0sel6 2 iot p spi pf11 spi1sel5 2 iot p spi pf10 spi0sel5 2 iot p spi spi pf spi1sel4 ssel1 3 io p spi s pf spi0sel4 ssel0 3 io p spi s pf7 spi1sel3 df 3 io p spi s , pll df1 2 df0 pll pf6 spi0sel3 msel6 3 io p spi s , pll s ck clkin pf5 spi1sel2 msel5 3 io p spi s , pll s ck clkin pf4 spi0sel2 msel4 3 io p spi s , pll s ck clkin pf3 spi1sel1 msel3 3 io p spi s , pll s ck clkin pf2 spi0sel1 msel2 3 io p spi s , pll s ck clkin pf1 spiss1 msel1 3 io p spi s , pll s ck clkin pf0 spiss0 msel0 3 io p spi s , pll s ck clkin rsclk0 2 iot r sport0 rfs0 2 iot r sport0 dr0 3 i s sport0 tsclk0 2 iot t sport0 tfs0 2 iot t sport0 dt0 o s sport0 t 7 p d c p t f
for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 20 rev. prc preliminary technical data rsclk1 2 i/o/t receive serial clock for sport1. rfs1 2 i/o/t receive frame synchr onization for sport1. dr1 3 i serial data receive for sport1. tsclk1 2 i/o/t transmit serial clock for sport1. tfs1 2 i/o/t transmit frame sync hronization for sport1. dt1 o serial data transmit for sport1. mosi0 2 i/o master out slave in pin for spi0. supplies the ou tput data from the master device and receives the input data to a slave device. miso0 2 i/o master in slave out pin for spi0. supplies the output da ta from the slave device and receives the input data to the master device. sck0 4 i/o clock line for spi0. master device output clock signal. sl ave device input clock signal. mosi1 2 i/o master out slave in pin for spi1. supplies the ou tput data from the master device and receives the input data to a slave device. miso1 2 i/o master in slave out pin for spi1. supplies the output da ta from the slave device and receives the input data to the master device. sck1 4 i/o clock line for spi1. master device output clock signal. sl ave device input clock signal. rx0 3 i uart0 receive pin. tx0 o uart0 transmit pin. rx1 3 i uart1 receive pin. tx1 o uart1 transmit pin. usb_clk 4 iusb clock. xver_data 4 i single ended receive data output from usb transceiver to the usbd module. dpls 4 i differential d+ receive data output from the usb transceiver to the ubd module. dmns 4 i differential d- receive data output from the usb trans ceiver to the usbd module. txdpls o transmitted d+ from the us bd module to the usb transceiver. txdmns o transmitted d- from the usbd module to the usb transceiver. txen o t usbd usb suspend o s usbd usb t sc nmi 4 i n- tck 2 itag tdo ot tag tdi 2 itag tms 2 i t trst 4 itag t 7 p d c p t f
preliminary technical data this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 21 rev. prc for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 reset i w 10 clkin , t - 40 clkin1 i c bypass i d m dd ss b - pll deepsleep o d b dsp c d-s bmode20 i d m dd ss c pci_ad310 2 iot pci pci_cbe3C0 2 iot pci pci_frame 2 iot pci u pci pci pci_irdy 2 iot pci pci_trdy 2 iot pci pci_desel 2 iot pci a pci pci_stop 2 iot pci pci_perr 2 iot pci pci_par 2 iot pci pci_req o pci u pci pci_serr 2 iot pci r pci_rst 2 iot pci pci_gnt 2 i pci u pci pci_idsel 4 i pci i pci - pci_lock 2 i pci u pci pci_clk 4 ipci pci_inta 2 iot pci a pci a adsp-21535 m adsp-21535 pci_intb 2 i pci b m adsp- 21535 pci_intc 2 i pci c m adsp-21535 pci_intd 2 i pci d m adsp-21535 xtali i r-t c xtalo o r-t c t 7 p d c p t f
for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 22 rev. prc preliminary technical data emu o e , m adsp-21535 ddpll p pll 15 ddrtc p r-t c 33 ddext p io x pci 33 ddpciext p pci io 33 ddint p i 15 gnd g p 1 p - 2 p , 3 p , 4 p , t 7 p d c p t f
preliminary technical data this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 23 rev. prc for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 adsp-21535?specifications recommended operating conditions parameter 1 1 specifications subject to change without notice. k grade parameter min nominal max unit v ddint internal (core) supply voltage 0.86 1.5 1.575 v v ddext external (i/o) supply voltage 2.5 3.3 3.45 v v ddpll pll power supply voltage 1.425 1.5 1.575 v v ddrtc real time clock power supply voltage 2.60 3.3 3.45 v v ddpciext pci i/o power supply voltage 3.15 3.3 3.45 v v ih high level input voltage 2 , @ v ddext =max 2 applies to input and bidirectional pins, except pci. 2.0 v ddext +0.5 v v il low level input voltage 2 , @ v ddext =min ?0.3 0.6 v v ihpci high level input voltage 3 , @ v ddext =max 3 applies to pci input and bidirectional pins: pci_ad31? 0, pci_cbe3 C 0 , pci_frame , pci_irdy , pci_trdy , pci_desel, pci_stop , pci_perr , pci_par, pci_serr , pci_rst , pci_gnt , pci_idsel , pci_lock , pci_clk, pci_inta , pci_intb , pci_intc , pci_intd 05 ddpciext ddpciext 05 ilpci l l i 3 , ddint 05 03 ddpciext t case c o t 0 5 c electrical caracteristics p 1 1 s t c m mx u o l o 2 2 a , x pci ddext , i o 05 a 24 ol l l o 2 ddext , i ol 20 a 04 opci pci l o 3 3 a pci pci_ad310, pci_cbe3C0 , pci_frame , pci_irdy , pci_trdy , pci_desel, pci_stop , pci_perr , pci_par, pci_req , pci_serr , pci_rst , pci_inta ddext , i o 05 a 0 ddpciext olpci pci l l o 3 ddext , i ol 15a 01 ddpciext i i l i c 4 4 a ddext x, in dd x tbd a i il l l i c 4 ddext x, in 0 tbd a i o t-s l c 5 5 a - ddext x, in dd x tbd a i ol t-s l c 5 ddext x, in 0 tbd a c in i c 6, 7 6 a 7 g, in 1 m, t case 25c, in 25 tbd f
for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 24 rev. prc preliminary technical data absolute maximum ratings esd sensitivity timing specifications table 8 and table 9 describe the timing requirements for the adsp -21535 clocks. take care in selecting msel and ssel ratios so as not to exceed the maximum core clock and system clock operating frequencies, as described in absolute maximum ratings . table 9 describes phase-locked loop operating conditions. internal (core) supply voltage (v ddint ) 1 . . ?0.3 v to +1.8 v 1 stresses greater than those listed above may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions greater than those indica ted in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. external (i/o) supply voltage (v ddext ) . . . ?0.3 v to +4.0 v input voltage. . . . . . . . . . . . . . . . . . ?0.5 v to v ddext +0.5 v output voltage swing . . . . . . . . . . . ?0.5 v to v ddext +0.5 v load capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pf core clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 mhz peripheral clock (sclk) . . . . . . . . . . . . . . . . . . 133 mhz storage temperature range. . . . . . . . . . . ?65oc to +150oc lead temperature (5 seconds). . . . . . . . . . . . . . . . . .185oc caution esd (electrostatic discharge) sensitive devi ce. electrostatic charges as high as 4000v readily accumulate on the hu man body and test equipmen t and can discharge without detection. although the adsp-21535 featur es proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precaut ions are recommended to avoid perfor- mance degradation or loss of functionality. table 8. core and system clock requirements parameter description min max unit t cclk1.5 core cycle period (v ddint =1.5 v?5%) 3.3 tbd ns t cclk1.4 core cycle period (v ddint =1.4 v?5%) tbd tbd ns t cclk1.3 core cycle period (v ddint =1.3 v?5%) tbd tbd ns t cclk1.2 core cycle period (v ddint =1.2 v?5%) tbd tbd ns t cclk1.1 core cycle period (v ddint =1.1 v?5%) tbd tbd ns t cclk1.0 core cycle period (v ddint =1.0 v?5%) tbd tbd ns t cclk0.9 core cycle period (v ddint =0.9 v?5%) tbd tbd ns f cclknn core clock frequency at t cclknn 1/t cclknn hz t sclk system clock period max. of (7.5 or t cclknn 2) ns f sclk system clock frequency 1/t sclk hz table 9. phase-locked loop operating conditions parameter min nominal max unit operating voltage 1.425 1.5 1.575 v jitter, rising edge to rising edge, per output 120 ps jitter, rising edge to falling edge, per output 60 ps
preliminary technical data this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 25 rev. prc for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 skew, rising edge to rising edge, any two outputs 120 ps voltage controlled oscillator (vco) frequency 40 400 mhz v ddpll induced jitter 1 ps/mv table 9. phase-locked loop operating conditions (continued) parameter min nominal max unit
for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 26 rev. prc preliminary technical data clock and reset timing table 10 and figure 12 describe clock and reset operations. per absolute maximum ratings on page 24 , com- binations of clkin and clock multipliers must not se lect core/peripheral clocks in excess of 300/133 mhz. table 10. clock and reset timing parameter description min max unit timing requirement s t ckin clkin period 30.0 100.0 ns t ckinl clkin low pulse 1 1 applies to bypass mode and non-bypass mode. 10.0 ns t ckinh clkin high pulse 1 10.0 ns t wrst reset a p l 2 2 a - a -, - 2000 clkin , reset , clkin - x 11 t ckin ns t pfd delay from reset a pfx io t 3 3 f , mselx df tbd msd d reset a mselx df 4 4 mselx df , tbd mss mselxdfbypass s s b reset d 5 5 mselx df , x tbd ms mselxdfbypass s a reset d tbd switching characteristics t sclkd clkout delay from clkin tbd tbd ns t sclk clkout period 6 6 the figure below shows a 2 ratio between t ckin and t sclk , but the ratio has many programmable options. for more information, see the system design chapter of the adsp-21535 dsp hardware reference . 7.5 ns figure 12. clock and reset timing t sclkd clkout msel6?0 bypass df reset clkin t wrst t ckinh t ckin t ckinl t msh t sclk t pfd t msd t mss
preliminary technical data this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 27 rev. prc for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 programmable flags cycle timing table 11 and figure 13 describe programmable flag operations. table 11. programmable flags cycle timing parameter description min max unit switching characteristic t dfo flag output delay with respect to sclk 6 ns t hfo flag output hold after sclk high tbd tbd ns timing requirement t hfi flag input hold is asynchronous 3 ns figure 13. programmable flags cycle timing flag input pf (input) t hfi pf (output) sclk flag output t dfo t dfo
for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 28 rev. prc preliminary technical data timer pwm_out cycle timing table 12 and figure 14 describe timer expired operations. the input signal is asynchrono us in ?width capture mode? and has an absolute maximum input frequency of tbd mhz. table 12. timer pwm_out cycle timing parameter description min max unit switching characteristic t hto timer pulsewidth output 1 1 the minimum time for t hto is one cycle, and the maximum time for t hto equals (2 32 ?1) cycles. 7.5 (2 32 ?1) cycles ns figure 14. timer pwm_out cycle timing sclk pwm_out t hto
preliminary technical data this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 29 rev. prc for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 asynchronous memory write cycle timing table 13. asynchronous memory write cycle timing parameter description min max unit timing requirements t sardy ardy setup before clkout 5.5 ns t hardy ardy hold after clkout 0.0 ns t ddat data31?0 disable after clkout 6.0 ns t endat data31?0 enable after clkout 1.0 ns switching characteristic t do output delay after clkout 1 1 output pins include ams3C0, abe3C0 , addr252, data310, aoe, awe 60 o o a clkout 1 0 figure 15. asynchronous memory write cycle timing t do t endat clkout amsx abe1?0 t ho be, address write data t ddat data15?0 awe t sardy t hardy setup 2cycles programmed read access 2 cycles access extended 1cycle hold 1cycle ardy addr19?1
for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 30 rev. prc preliminary technical data asynchronous memory read cycle timing table 14. asynchronous memory read cycle timing parameter description min max unit timing requirements t sdat data31?0 setup before clkout 2.1 ns t hdat data31?0 hold after clkout 0.8 ns t sardy ardy setup before clkout 5.5 ns t hardy ardy hold after clkout 0.0 ns switching characteristic t do output delay after clkout 1 1 output pins include ams3C0, abe3C0 , addr252, aoe , are 60 o o a clkout 1 0 figure 16. asyn chronous memory read cycle timing t do t sdat clkout amsx abe1?0 t ho be, address read t hdat data15?0 aoe t do t sardy t hardy setup 2cycles programmed read access 4cycles access extended 3cycles hold 1cycle are t hardy ardy addr19?1
preliminary technical data this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 31 rev. prc for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 sdram interface timing table 15. sdram interface timing parameter description min max unit timing requirement t ssdat data setup before clkout 2.1 ns t hsdat data hold after clkout 0.8 ns switching characteristic t sclk clkout period 7.5 ns t sclkh clkout width high tbd ns t sclkl clkout width low tbd ns t dcad command, addr, data delay after clkout 1 1 command pins include: sras , scas , swe , sdqm, sms , sa10, scke 60 cad c, addr, d a clkout 1 0 dsdat d d a clkout 60 ensdat d e a clkout 10 figure 17. sdram interface timing t hcad t hcad t dsdat t dcad t ssdat t dcad t ensdat t hsdat t sclkl t sclkh t sclk clkout data (in) data (out) cmnd 1 addr (out) notes 1 command = sras , scas , swe ,sdqm, sms , saio, scke.
for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 32 rev. prc preliminary technical data serial ports table 16. serial ports?external clock parameter description min max unit timing requirements t sfse tfs/rfs setup before tclk/rclk 1 1 referenced to sample edge. 3.0 ns t hfse tfs/rfs hold after tclk/rclk 1 3.0 ns t sdre receive data setup before rclk 1 3.0 ns t hdre receive data hold before rclk 1 3.0 ns t sclkw tclk/rclk width 4.5 ns t sclk tclk/rclk period 15.0 ns table 17. serial ports?internal clock parameter description min max unit timing requirements t sfsi tfs/rfs setup before tclk/rclk 1 1 referenced to sample edge. 7.0 ns t hfsi tfs/rfs hold after tclk/rclk 1 2.0 ns t sdri receive data setup before rclk 1 7.0 ns t hdri receive data hold before rclk 1 4.0 ns table 18. serial ports?ex ternal or internal clock parameter description min max unit switching characteristics t dfse rfs delay after rclk (internally generated rfs) 1 1 referenced to drive edge. 10.0 ns t hofse rfs hold after rclk (internally generated rfs) 1 6.0 ns table 19. serial ports?external clock parameter description min max unit switching characteristics t dfse tfs delay after tclk (internally generated tfs) 1 1 referenced to drive edge. 10.0 ns t hofse tfs hold after tclk (internally generated tfs) 1 6.0 ns t ddte transmit data delay after tclk 1 10.0 ns t hdte transmit data hold after tclk 1 6.0 ns table 20. serial ports?internal clock parameter description min max unit switching characteristics t dfs i tfs delay after tclk (internally generated tfs) 1 1 referenced to drive edge. 4.0 ns t hofs i tfs hold after tclk (internally generated tfs) 1 0.0 ns t ddt i transmit data delay after tclk 1 4.0 ns t hdt i transmit data hold after tclk 1 0.0 ns t sclkiw tclk/rclk width 4.5 ns
preliminary technical data this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 33 rev. prc for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 table 21. serial ports?enable and three-state parameter description min max unit switching characteristics t dtene data enable delay from external tclk 1 5.0 ns t ddtte data disable delay from external tclk 1 12.0 ns t dteni data enable delay from internal tclk 2.0 ns t ddtti data disable delay from internal tclk 1 5.0 ns 1 referenced to drive edge.
for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 34 rev. prc preliminary technical data figure 18. serial ports dt dt t ddtte t ddten t ddtti t ddtin drive edge drive edge drive edge drive edge tclk / rclk tclk / rclk tclk (ext) tfs ("late", ext.) tclk (int) tfs ("late", int.) t sdri rclk rfs dr drive edge sample edge t hdri t sfsi t hfsi t dfse t hofse t sclkiw data receive- internal clock t sdre data receive- external clock rclk rfs dr drive edge sample edge t hdre t sfse t hfse t dfse t sclkw t hofse note: either the rising edge or falling edge of rclk, tclk can be used as the active sampling edge. t ddti t hdti tclk tfs dt drive edge sample edge t sfsi t hfsi t sclkiw t dfsi t hofsi data transmit- internal clock t ddte t hdte tclk tfs dt drive edge sample edge t sfse t hfse t dfse t sclkw t hofse data transmit- external clock note: either the rising edge or falling edge of rclk or tclk can be used as the active sampling edge.
preliminary technical data this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 35 rev. prc for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 serial peripheral interfac e (spi) port?master timing table 22 and figure 19 describe spi port master operations. table 22. serial peripheral interface (spi) port?master timing parameter description min max unit timing requirements t sspid data input valid to sclk edge (data input setup) 1.6 ns t hspid sclk sampling edge to data input invalid 1.6 ns switching characteristics t sdscim spixsel sclk x0 1 2 sclk spicm s 2 sclk spiclm s 2 sclk spiclk s 4 sclk dsm l sclk spixsel x0 1 2 sclk spitdm s 2 sclk ddspid sclk 0 6 dspid sclk 0 5 figure 19. serial peripheral interface (spi) port?master timing t sspid t hspid t hdspid lsb msb t hspid t ddspid mosi (output) miso (input) spixsel (output) (x = 0 or 1) sclk (cpol = 0) (output) sclk (cpol = 1) (output) t spichm t spiclm t spi - clm t spiclk t spichm t hdsm t spitdm t hdspid lsb valid lsb msb msb valid t hspid t ddspid mosi (output) miso (input) t sspid cpha=1 cpha=0 msb valid t sdscim t sspid lsb valid
for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 36 rev. prc preliminary technical data serial peripheral interface (spi) port?slave timing table 23 and figure 20 describe spi port slave operations. table 23. serial peripheral interface (spi) port?slave timing parameter description min max unit timing requirements t spichs serial clock high period 2t sclk ns t spicls serial clock low period 2t sclk ns t spiclk serial clock period 4t sclk ns t hds last spiclk edge to spiss 2 sclk spitds s t d 2 sclk sdsci spiss sclk 2 sclk sspid d sclk 16 spid sclk 16 switching characteristics t dsoe spiss 06 dsdi spiss 06 ddspid sclk 0 5 dspid sclk 0 5 figure 20. serial peripheral interface (spi) port?slave timing t hspid t ddspid t dsdhi lsb msb msb valid t hspid t dsoe t dds - pid t hdspid miso (output) mosi (input) t sspid spiss (input) sclk (cpol = 0) (input) sclk (cpol = 1) (input) t sdsci t spichs t spicls t spicls t spiclk t hds t spichs t sspid t hspid t dsdhi lsb valid msb msb valid t dsoe t ddspid miso (output) mosi (input) t sspid lsb valid lsb cpha=1 cpha=0 t spitds
preliminary technical data this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 37 rev. prc for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 universal asynchronous receiver-transmitter (uart) port?receive and transmit timing figure 21 describes uart port receive and transmit operations . the maximum baud rate is sclk/16. as shown in figure 21 there is some latency between the generation internal uart interrupts and the exte rnal data operations. these latencies are negligible at the data transmission rates for the uart. figure 21. uart port?rec eive and transmit timing rxd data(5?8) internal uart receive interrupt uart receive bit set by data stop; cleared by fifo read sclk (sample clock) txd data(5?8) stop (1?2) internal uart transmit interrupt uart transmit bit set by program; cleared by write to transmit start stop transmit receive as data writen to buffer
for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 38 rev. prc preliminary technical data jtag test and emulation port timing table 24 and figure 22 describe jtag port operations. table 24. jtag port timing parameter description min max unit timing parameters t tck tck period 20 ns t stap tdi, tms setup before tck high 4 ns t htap tdi, tms hold after tck high 4 ns t ssys system inputs setu p before tck low 1 1 system inputs=data31-0, addr25- 2, ardy, tmr2-0, pf15-0, rsclk0 , rfs0, dr0, tsclk0, tfs0, rsclk 1, rfs1, dr1, tsclk1, tfs1, mosi0, miso0, sck0, mosi1, miso1, sck1, rx 0, rx1, tsb_clk, xver_data, dpls, dmns, nmi, reset , bypass, bmode2-0, pci_ad31-0, pci_cbe3-0 , pci_frame , pci_irdy , pci_trdy , pci_desel, pci_stop , pci_perr , pci_par, pci_serr , pci_rst , pci_gnt , pci_idsel , pci_lock , pci_clk, pci_inta , pci_intb , pci_intc , pci_intd 4 sys s i a tck l 1 5 trstw trst p 2 2 50 m x 4 switching characteristics t dtdo tdo delay from tck low 4 ns t dsys system outputs delay after tck low 3 3 system outputs=data31-0, addr25-2, abe sdqm3-0, aoe , are , awe , clkoutsclk1, sclk0, scke, sa10, sras , scas , swe , sms3-0 , tmr2-0, pf15-0, rsclk0, rfs0, ts clk0, tfs0, dt0, rsclk1, rfs1, tsclk1, tfs1, dt 1, mosi0, miso0, sck0 , mosi1, miso1, sck1, tx0, tx1, txdpls, txdmns, txen , suspend, deepsleep, pci_ad31-0, pci_cbe3-0 , pci_frame , pci_irdy , pci_trdy , pci_desel, pci_stop , pci_perr , pci_par, pci_req , pci_serr , pci_rst , pci_inta , emu 05 figure 22. jtag port timing tms tdi tdo system inputs system outputs tck t tck t htap t stap t dtdo t ssys t hsys t dsys
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 39 rev. prc for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 preliminary technical data power dissipation total power dissipation has two components, one due to internal circuitry (p int ) and one due to the switching of external output drivers (p ext ). table 25 shows the power dissipation for internal circuitry. internal power dissipation is dependent on the instructio n execution sequence and the data operands involved. table 26 lists the conditions under which the values in table 25 are obtained. the external component of tota l power dissipation is caused by the switching of output pins. its magnitude depends on ? ? ? ? p ext =o c v dd f the frequency f includes driving the load high and then back low. for example: data31?0 pins can drive high and low at a maximum rate of 1/(2 t sclk ) while in sdram burst mode. a typical power consumption can now be calculated for these conditions by adding a typical internal power dissipa- tion. p total =p ext +(i dd v ddint ) note that the conditions causing a worst-case p ext differ from those causing a worst-case p int . maximum p int cannot occur while 100% of the output pins are switching from all ones (1s) to all zeros (0s). note also that it is not common for an application to have 100% ,or even 50%, of the outputs switching simultaneously. environmental conditions the adsp-21535 is offered in a 260-lead pbga package. the adsp-21535 is specified for a case temperature (t case ). to ensure that t case is not exceeded, an airflow source may be used. t case is calculated using t case =t amb +(pd ca ) t case = case temperature (measured on top surface of package pd = power dissipation in w (this value depends upon the specific application) table 25. internal power dissipation parameter test conditions typical (v ddint =1.5 v) 1 typical (v ddint =1.0 v) 1 units i ddhigh t cclkmin , 25oc tbd tbd ma i ddtyp t cclkmin , 25oc tbd tbd ma i ddlow t cclkmin , 25oc tbd tbd ma i ddsys t cclkmin , 25oc tbd tbd ma i ddefr t cclkmin , 25oc tbd tbd ma i ddactive 25oc tbd tbd ma i ddsleep 25oc tbd tbd ma i dddeepsleep 25oc tbd tbd ma 1 typical idd data is specified for nominal v ddint and typical process parameters.maximum i dd is within tbd% of typical values. table 26. internal power dissipation conditions parameter mode pll cclk sclk activity i ddhigh 1 full-on enabled enabled enabled tbd i ddtyp 1 full-on enabled enabled enabled tbd i ddlow 1 full-on enabled enabled enabled tbd i ddsys 2 full-on enabled enabled enabled tbd i ddefr 3 full-on enabled enabled enabled algorithm-dependent i ddactive active enabled/bypass ed enabled enabled tbd i ddsleep sleep enabled disabled enabled tbd i dddeepsleep deep-sleep disabled di sabled disabled tbd 1 tbd instruction mix. 2 tbd instruction mix and system dma every cycle. 3 implementation of enhanced full rate (efr) gsm algorithm, inst ruction and data fetch from l1/l2 memories and cache.
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 40 rev. prc for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 preliminary technical data see table 27 for three instances of li near feet per minute of airflow. adsp-21535 260-lead pbga pinout table 28 lists the pbga pinout by signal name. table 29 on page 43 lists the pinout by pin number. table 27. airflow linear ft/min 0 200 400 ca (oc/w) tbd tbd tbd table 28. 260-lead pbga pin assignment (alphabetically by signal) signal pin # abe0 sdqm0 e02 abe1 sdqm1 b01 abe2 sdqm2 g03 abe3 sdqm3 07 addr2 a06 addr3 b06 addr4 d06 addr5 c06 addr6 a05 addr7 b05 addr a04 addr c05 addr10 d05 addr11 b04 addr12 a01 addr13 c04 addr14 d04 addr15 a03 addr16 b03 addr17 a02 addr1 c03 addr1 d03 addr20 b02 addr21 c02 addr22 e03 addr23 c01 addr24 f03 addr25 d02 ams0 f02 ams1 d01 ams2 03 ams3 g02 aoe e01 ardy r01 are f01 awe g01 bmode0 b14 bmode1 a14 bmode2 b13 bypass c12 clkin1 d0 clkoutsclk1 01 data0 n02 data1 m03 data2 t01 data3 p02 data4 n03 data5 r02 data6 p03 data7 u01 data u02 data t02 data10 02 data11 03 data12 r04 data13 u03 data14 t03 data15 t04 data16 u04 data17 04 data1 05 data1 r05 data20 t05 data21 u05 data22 06 data23 r06 data24 u06 data25 t06 data26 07 data27 0 data2 u07 data2 r07 data30 t07 data31 0 dmns d0 dpls c0 dr0 14 dr1 u15 dt0 r14 dt1 17 emu a13 gnd c13 gnd 02 gnd 0 gnd 10 gnd 11 gnd 07 gnd 0 gnd 0 t 2 260-l pbga p a a s c signal pin
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 41 rev. prc for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 preliminary technical data gnd j10 gnd j11 gnd j12 gnd k02 gnd k07 gnd k08 gnd k09 gnd k10 gnd k11 gnd k12 gnd l07 gnd l08 gnd l09 gnd l10 gnd l11 gnd m07 gnd m09 gnd m10 miso0 t16 miso1 u18 mosi0 u16 mosi1 t17 n/c a18 n/c r03 n/c v01 n/c v18 nmi b11 pci_ad0 e17 pci_ad1 e18 pci_ad2 g16 pci_ad3 f17 pci_ad4 f18 pci_ad5 g18 pci_ad6 g17 pci_ad7 h18 pci_ad8 j18 pci_ad9 h17 pci_ad10 k18 pci_ad11 h16 pci_ad12 l18 pci_ad13 j17 pci_ad14 m18 pci_ad15 k17 pci_ad16 j16 pci_ad17 k16 pci_ad18 n18 pci_ad19 p18 pci_ad20 l17 pci_ad21 l16 pci_ad22 r18 pci_ad23 t18 table 28. 260-lead pbga pin assignment (alphabetically by signal) (continued) signal pin # pci_ad24 m17 pci_ad25 m16 pci_ad26 n17 pci_ad27 p17 pci_ad28 p15 pci_ad29 n16 pci_ad30 r17 pci_ad31 p16 pci_cbe0 f16 pci_cbe1 f15 pci_cbe2 e16 pci_cbe3 d17 pci_clk d14 pci_desel c16 pci_frame c17 pci_gnt c1 pci_idsel b1 pci_inta c14 pci_intb b15 pci_intc a15 pci_intd d13 pci_irdy e15 pci_lock a16 pci_par c15 pci_perr d15 pci_req d16 pci_rst d1 pci_serr b16 pci_stop a17 pci_trdy b17 pf0 spiss0 msel0 u0 pf1 spiss1 msel1 r0 pf2 spi0sel1 msel2 t0 pf3 spi1sel1 msel3 10 pf4 spi0sel2 msel4 u0 pf5 spi1sel2 msel5 r0 pf6 spi0sel3 msel6 t0 t 2 260-l pbga p a a s c signal pin
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 42 rev. prc for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 preliminary technical data pf7 / spi1sel3 df r11 pf spi0sel4 ssel0 t11 pf spi1sel4 ssel1 u11 pf10 spi0sel5 12 pf11 spi1sel5 t12 pf12 spi0sel6 r12 pf13 spi1sel6 u12 pf14 spi0sel7 13 pf15 spi1sel7 t13 reset b0 rfs0 u13 rfs1 16 rsclk0 r13 rsclk1 u14 rx0 a07 rx1 b0 sa10 m01 scas l03 sck0 u17 sck1 r16 scke l01 sclk0 k01 sleep d12 sms0 m02 sms1 p01 sms2 n01 sms3 k03 sras l02 suspend a11 swe 03 tck d10 tdi c11 tdo d11 tfs0 t14 tfs1 r15 tmr0 b07 tmr1 c07 tmr2 d07 tms a12 t 2 260-l pbga p a a s c signal pin trst b12 tsclk0 15 tsclk1 t15 tx0 a0 tx1 c0 txdmns g10 txdpls b10 txen c10 usb_clk g07 ddext e04 ddext g04 ddext g0 ddext 01 ddext 02 ddext 04 ddext k04 ddext l04 ddext m04 ddext p04 ddint f04 ddint g11 ddint g12 ddint g15 ddint 04 ddint 0 ddint 12 ddint l12 ddint m0 ddint m11 ddint m12 ddint n04 ddint n15 ddpciext 15 ddpciext 15 ddpciext k15 ddpciext l15 ddpciext m15 ddpll g0 ddrtc u10 sspll a10 ssrtc 11 xtali r10 xtalo t10 xer_data a0 t 2 260-l pbga p a a s c signal pin
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 43 rev. prc for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 preliminary technical data table 29. 260-lead pbga pin assignment (numerically by pin number) pin # signal a01 addr12 a02 addr17 a03 addr15 a04 addr8 a05 addr6 a06 addr2 a07 rx0 a08 tx0 a09 xver_data a10 v sspll a11 suspend a12 tms a13 emu a14 bmode1 a15 pci_intc a16 pci_lock a17 pci_stop a1 nc b01 abe1 sdqm1 b02 addr20 b03 addr16 b04 addr11 b05 addr7 b06 addr3 b07 tmr0 b0 rx1 b0 reset b10 txdpls b11 nmi b12 trst b13 bmode2 b14 bmode0 b15 pci_intb b16 pci_serr b17 pci_trdy b1 pci_idsel c01 addr23 c02 addr21 c03 addr1 c04 addr13 c05 addr c06 addr5 c07 tmr1 c0 tx1 c0 dpls c10 txen c11 tdi c12 bypass c13 gnd c14 pci_inta c15 pci_par c16 pci_desel c17 pci_frame c1 pci_gnt d01 ams1 d02 addr25 d03 addr1 d04 addr14 d05 addr10 d06 addr4 d07 tmr2 d0 dmns d0 clkin1 d10 tck d11 tdo d12 sleep d13 pci_intd d14 pci_clk d15 pci_perr d16 pci_req d17 pci_cbe3 d1 pci_rst e01 aoe e02 abe0 sdqm0 e03 addr22 e04 ddext e15 pci_irdy e16 pci_cbe2 e17 pci_ad0 e1 pci_ad1 f01 are f02 ams0 f03 addr24 f04 ddint f15 pci_cbe1 f16 pci_cbe0 f17 pci_ad3 f1 pci_ad4 g01 awe g02 ams3 g03 abe2 sdqm2 g04 ddext g07 usb_clk g0 ddext g0 ddpll g10 txdmns g11 ddint g12 ddint g15 ddint g16 pci_ad2 g17 pci_ad6 g1 pci_ad5 t 2 260-l pbga p a n p n c pin signal
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 44 rev. prc for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 preliminary technical data h01 clkout/sclk1 h02 gnd h03 ams2 04 ddint 07 abe3 sdqm3 0 gnd 0 ddint 10 gnd 11 gnd 12 ddint 15 ddpciext 16 pci_ad11 17 pci_ad 1 pci_ad7 01 ddext 02 ddext 03 swe 04 ddext 07 gnd 0 gnd 0 gnd 10 gnd 11 gnd 12 gnd 15 ddpciext 16 pci_ad16 17 pci_ad13 1 pci_ad k01 sclk0 k02 gnd k03 sms3 k04 ddext k07 gnd k0 gnd k0 gnd k10 gnd k11 gnd k12 gnd k15 ddpciext k16 pci_ad17 k17 pci_ad15 k1 pci_ad10 l01 scke l02 sras l03 scas l04 ddext l07 gnd l0 gnd l0 gnd l10 gnd l11 gnd t 2 260-l pbga p a n p n c pin signal l12 ddint l15 ddpciext l16 pci_ad21 l17 pci_ad20 l1 pci_ad12 m01 sa10 m02 sms0 m03 data1 m04 ddext m07 gnd m0 ddint m0 gnd m10 gnd m11 ddint m12 ddint m15 ddpciext m16 pci_ad25 m17 pci_ad24 m1 pci_ad14 n01 sms2 n02 data0 n03 data4 n04 ddint n15 ddint n16 pci_ad2 n17 pci_ad26 n1 pci_ad1 p01 sms1 p02 data3 p03 data6 p04 ddext p15 pci_ad2 p16 pci_ad31 p17 pci_ad27 p1 pci_ad1 r01 ardy r02 data5 r03 nc r04 data12 r05 data1 r06 data23 r07 data2 r0 pf1 spiss1 msel1 r0 pf5 spi1sel2 msel5 r10 xtali t 2 260-l pbga p a n p n c pin signal
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 45 rev. prc for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 preliminary technical data r11 pf7 / spi1sel3 df r12 pf12 spi0sel6 r13 rsclk0 r14 dt0 r15 tfs1 r16 sck1 r17 pci_ad30 r1 pci_ad22 t01 data2 t02 data t03 data14 t04 data15 t05 data20 t06 data25 t07 data30 t0 pf2 spi0sel1 msel2 t0 pf6 spi0sel3 msel6 t10 xtalo t11 pf spi0sel4 ssel0 t12 pf11 spi1sel5 t13 pf15 spi1sel7 t14 tfs0 t15 tsclk1 t16 miso0 t17 mosi1 t1 pci_ad23 u01 data7 u02 data u03 data13 u04 data16 u05 data21 u06 data24 u07 data2 u0 pf0 spiss0 msel0 u0 pf4 spi0sel2 msel4 u10 ddrtc t 2 260-l pbga p a n p n c pin signal u11 pf spi1sel4 ssel1 u12 pf13 spi1sel6 u13 rfs0 u14 rsclk1 u15 dr1 u16 mosi0 u17 sck0 u1 miso1 01 nc 02 data10 03 data11 04 data17 05 data1 06 data22 07 data26 0 data27 0 data31 10 pf3 spi1sel1 msel3 11 ssrtc 12 pf10 spi0sel5 13 pf14 spi0sel7 14 dr0 15 tsclk0 16 rfs1 17 dt1 1 nc t 2 260-l pbga p a n p n c pin signal
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 46 rev. prc for current information contact analog devices at 800-262-5643 adsp-21535 june 2002 preliminary technical data outline dimensions dimensions in figure 23 are shown in millimeters. ordering guide figure 23. 260-lead metric plasti c ball grid array (pbga) (b-260) part number case temperature range instruction rate operating voltage ADSP-21535Pkb-300 0oc to 85oc 300 mhz 0.9 v to 1.5 v internal, 3.3 v i/o ADSP-21535Pbb-200 -40oc to +105oc 200 mhz 0.9 v to 1.5 v internal, 3.3 v i/o detail a 2.50 max seating plane 0.65 0.55 0.45 0.63 0.40 0.55 0.50 0.45 ball diameter 0.20 max, typ 1.22 max detail a top view ball a1 indicator 19.05 19.00 sq 18.95 17.05 16.95 sq 16.85 a b c d e f g h j k l m n p r t u v 15 13 11 9 7 5 3 1 17 16 14 12 10 8 6 4 2 18 bottom view 1.00 bsc ball pitch 17.00 bsc sq 1.00 bsc 1.00 bsc notes 1. all dimensions are in millimeters. 2. the actual position of the ball grid is within 0.25 of the ideal position relative to the package edges. 3. the actual position of each ball is within 0.10 of its ideal position relative to the ball grid. 4. center dimensions are nominal.

▲Up To Search▲

Price & Availability of ADSP-21535P

	To Download ADSP-21535P Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .